Technical Field
The present invention relates generally to semiconductor devices, and more specifically, to structures and methods of fabricating semiconductor devices using standard semiconductor cell fabrication.
Description of the Related Art
Standard semiconductor cell fabrication is a method for designing integrated circuits (ICs) for specific applications. Circuits are designed based on the desired functions using cells from a cell library, which are combined and constructed by a placement tool to result in the desired circuits. Standard semiconductor cell library performance is limited by the current a transistor of a cell can deliver. This is proportional to the width of the transistor. Thus, it is desirable to enable the transistor to be as wide as possible in a standard cell to deliver high performance circuits.
Standard cell methodology is a technique of designing ICs with a focus on the logic functions used in the IC. A standard cell includes multiple transistors that are interconnected to implement desired logic functions, such as AND, OR, NOT, XOR, and XNOR, as well as storage functions (e.g., flip-flops, latches, and buffers).
As semiconductor processes advance, device sizes continue to decrease. Present semiconductor production includes 14 nanometer and soon 7 nanometer minimum feature sizes. These process milestones are usually referred to as “technology nodes”. Advances towards 7 nanometer node mass production are underway and expected shortly. The trend to smaller devices and more advanced nodes will no doubt continue.
As the transistor sizes shrink commensurate with the advances in the technology nodes, the device characteristics and performance become dominated by physical layout effects. The devices also exhibit wide performance differences due to semiconductor process variations. Robust designs must anticipate these effects.
In order to control the device process variation sensitivity, semiconductor manufacturers can use a restricted design rule approach (“RDR”). By restricting where certain layers can be formed with respect to the cell boundaries and with respect to the other layers, the process variation sensitivity issue can be reduced. However, this approach produces additional disadvantages. If horizontal polysilicon routing is not available to the routing process, for example, a layer of metal, typically metal layer 2 must be used to connect internal devices together to form a simple function within a cell. This known prior art approach increases the parasitic coupling significantly, thereby slowing down circuit performance. Generally, an area penalty is created when RDR approaches are used. The amount of silicon needed to implement the cells increases as the design rules are restricted.
This additional metal 2 (M2 layer) routing within the cells also adversely uses most of the available metal 2 (M2 layer) connectivity resources. Further, because the base cells now include the M2 layer, a routing congestion issue can occur when trying to route inter-cell connection signals, or power, clock or ground signals, over the cells. The result is a larger (less dense) layout requiring additional silicon area, or requiring the use of additional metal layers to resolve the congestion problems. These solutions to congestion in the cells add to manufacturing costs.